Referring generally to FIGS. 1a–1e, shallow trench isolation (STI) is an enabling technology for the fabrication of advanced sub-micron integrated devices. A typical STI process sequence includes the following process steps: pad oxide oxidation, LPCVD nitride deposition, trench lithography, trench etch, resist strip/clean, liner oxidation, CVD oxide trench fill, planarization, post-chemical mechanical polishing (CMP) clean/light BHF dip, and nitride strip. This sequence describes STI related processes only and leaves out many other front-end processing steps.
Requirements for STI planarization are much more stringent than those for inter-layer dielectric (ILD) planarization. CMP has been accepted in recent years as a critical step in mainstream integrated circuit fabrication technology, and has enabled the fabrication of multi-level interconnection of up to 5 or 6 metal levels.
Superior isolation characteristics of STI enable scaling of active area pitches to the 0.5 mm regime. This, coupled with the additional advantages of better planarity, latch-up immunity, low junction capacitance, and a near-zero-field encroachment mandates the use of STI in advanced complementary metal-oxide semiconductor (CMOS) technologies.